Atsushi Kamo

Publication Activity (10 Years)

Years Active: 1998-2005
Publications (10 Years): 0

Publications

Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) (2005)
Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE (2004)
Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) (2002)
Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai
A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) (2002)
Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Masaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) (2001)
Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) (2001)
Atsushi Kamo, Takayuki Watanabe, Hideki Asai
Expanded GMC for transient analysis of transmission line networks. ISCAS (6) (1999)
Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai
Neural network simulator for spatiotemporal pattern analysis. ICECS (1998)