Teru Yoneyama

Publication Activity (10 Years)

Years Active: 1998-2003
Publications (10 Years): 0

Publications

Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai
A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. ISCAS (3) (2002)
Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai
Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai
A low voltage floating resistor having positive and negative resistance values. APCCAS (1) (2002)
Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Shashidhar Tantry, Teru Yoneyama, Hideki Asai
Two floating resistor circuits and their applications to synaptic weights in analog neural networks. ISCAS (1) (2001)
Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya
Design Method of Limit Cycle Generator by Hysteresis Neural Networks. IJCNN (3) (2000)
Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai
Design method of neural networks for limit cycle generator. IJCNN (1999)
Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai
Neural network simulator for spatiotemporal pattern analysis. ICECS (1998)