Takeshi Nakayama

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 6

Top Topics

Error Compensation

Human Knowledge

Multi Path Routing

Top Venues

IEICE Trans. Commun.

IEEE Trans. Biomed. Circuits Syst.

IPIN (Short Papers/Work-in-Progress Papers)

Publications

Abudusaimi Abuduaini, Nobuyuki Shiraki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
Frequency Error Compensation of Unsynchronized Bistatic CW- MIMO Radar for Multiple Human-Body Localization. IEEE Trans. Biomed. Circuits Syst. 16 (5) (2022)
Nobuyuki Shiraki, Naoki Honma, Kentaro Murata, Takeshi Nakayama, Shoichi Iizuka
Estimation Method of the Number of Targets Using Cooperative Multi-Static MIMO Radar. IEICE Trans. Commun. (12) (2021)
Shoichi Iizuka, Takeshi Nakayama, Dai Sasakawa, Naoki Honma
Non-restraint human authentication using MIMO array. IPIN (Short Papers/Work-in-Progress Papers) (2019)
Dai Sasakawa, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
Human Activity Identification by Height and Doppler RCS Information Detected by MIMO Radar. IEICE Trans. Commun. (7) (2019)
Katsumi Sasaki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
RSSI-Based Living-Body Radar Using Single RF Front-End and Tunable Parasitic Antennas. IEICE Trans. Commun. (2) (2018)
Dai Sasakawa, Naoki Honma, Kentaro Nishimori, Takeshi Nakayama, Shoichi Iizuka
Evaluation of fast human localization and tracking using MIMO radar in multi-path environment. PIMRC (2016)
Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane
AND-type 512-Mb flash memory with 1.8-V power supply. IEEE J. Solid State Circuits 36 (11) (2001)
Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. IEEE J. Solid State Circuits 34 (11) (1999)
Jien Kato, Toyohide Watanabe, Takeshi Nakayama, Lishing Guo, Hitoshi Kato
A model-based approach for recognizing folding process of origami. ICPR (1998)
Jien Kato, Toyohide Watanabe, Takeshi Nakayama
Recognition of Essential Folding Operations: A Step for Interpreting Illustrated Books of Origami. ICDAR (1997)
Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN (1997)
Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya
Tiling algorithm with fitting violation function for analog neural array. ICNN (1996)
Qin Luo, Takahiro Watanabe, Takeshi Nakayama
Identifying contents page of documents. ICPR (1996)
Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai
Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN (1995)
Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits 29 (4) (1994)