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Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi KobayashiHiroaki NakaiYuichi KunoriTakeshi NakayamaYoshikazu MiyawakiYasushi TeradaHiroshi OnodaNatsuo AjikaMasahiro HatanakaHirokazu MiyoshiTsutomu Yoshihara
Published in: IEEE J. Solid State Circuits (1994)
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