Debora Matos

Publication Activity (10 Years)

Years Active: 2009-2016
Publications (10 Years): 2

Top Topics

Multi Processor

Fault Tolerance

Hierarchical Structure

Top Venues

Publications

Rodrigo Cataldo, Guilherme Korol, Ramon Fernandes, Debora Matos, César A. M. Marcon
Architectural exploration of Last-Level Caches targeting homogeneous multicore systems. SBCCI (2016)
Rodrigo Cataldo, Guilherme Korol, Ramon Fernandes, Gustavo Sanchez, Debora Matos, César A. M. Marcon
Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark. ICECS (2016)
Debora Matos, Max Prass, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin
Performance evaluation of hierarchical NoC topologies for stacked 3D ICs. ISCAS (2015)
Debora Matos, Márcio Eduardo Kreutz, Cezar Reinbrecht, Luigi Carro, Altamiro Amadeu Susin
Adaptive multiple switching strategy toward an ideal NoC. ISCAS (2014)
Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. VLSI-SoC (2013)
Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Amadeu Susin
Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability. ARC (2013)
Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Márcio Eduardo Kreutz, Fernanda Gusmão de Lima Kastensmidt, Altamiro Amadeu Susin
A NOC closed-loop performance monitor and adapter. Microprocess. Microsystems 37 (6-7) (2013)
Anelise Kologeski, Caroline Concatto, Debora Matos, Daniel Grehs, Tiago Motta, Felipe Almeida, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Ricardo Reis
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip. ICECS (2013)
Debora Matos, Cezar Reinbrecht, Gianluca Palermo, Jonathan Martinelli, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro
Floorplan-aware hierarchical NoC topology with GALS interfaces. ISCAS (2012)
Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. DATE (2011)
Debora Matos, Gianluca Palermo, Vittorio Zaccaria, Cezar Reinbrecht, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip. NoCArc@MICRO (2011)
Debora Matos, Caroline Concatto, Márcio Eduardo Kreutz, Fernanda Lima Kastensmidt, Luigi Carro, Altamiro Amadeu Susin
Reconfigurable Routers for Low Power and High Performance. IEEE Trans. Very Large Scale Integr. Syst. 19 (11) (2011)
Debora Matos, Miklecio Costa, Luigi Carro, Altamiro Amadeu Susin
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip. VLSI-SoC (2010)
Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz
Monitor-adapter coupling for NOC performance tuning. ICSAMOS (2010)
Debora Matos, Luigi Carro, Altamiro Amadeu Susin
Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs. ISCAS (2010)
Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz
Adaptive router architecture based on traffic behavior observability. NoCArc@MICRO (2009)
Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. SBCCI (2009)
Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz
NoC Power Optimization Using a Reconfigurable Router. ISVLSI (2009)
Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin
The Need for Reconfigurable Routers in Networks-on-Chip. ARC (2009)