A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.
Luca SterponeLuigi CarroDebora MatosStephan WongF. FakharPublished in: DATE (2011)
Keyphrases
- low power
- power reduction
- power consumption
- low cost
- field programmable gate array
- reconfigurable hardware
- high speed
- digital signal processing
- power dissipation
- power saving
- smart camera
- embedded systems
- low power consumption
- hardware implementation
- energy efficiency
- power management
- logic circuits
- gate array
- real time
- image processing
- hardware and software
- image sensor
- energy saving
- parallel computing
- image processing algorithms
- energy consumption
- data center
- wireless sensor networks