Daewoong Lee

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 10

Top Topics

Infinite Impulse Response

Agnostic Learning

Power Consumption

Data Generation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC (2024)
Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, Daehyun Kwon, Chulhee Cho, Sang-Hoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, Hyoung-Joo Kim, Ho-Seok Seol, Juhwan Kim, Jung-Bum Shin, Gil-Young Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, ChanYong Lee, Seungseob Lee, TaeHoon Park, Chi-Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-Young Oh, SangJoon Hwang, Kyung Suk Oh, Jung-Hwan Choi, Jooyoung Lee
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. IEEE J. Solid State Circuits 58 (1) (2023)
Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho, Sanghoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, HyoungJoo Kim, Ho-Seok Seol, Juhwan Kim, Junabum Shin, Kil-Youna Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, ChanYong Lee, Seungseob Lee, TaeHoon Park, Chi Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-Young Oh, SangJoon Hwang, Kyung Suk Oh, Jung-Hwan Choi, JooYoung Lee
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. ISSCC (2022)
Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. VLSI Circuits (2019)
Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. ICCAD (2019)
Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Yong-Hun Kim, Dongil Lee, Daewoong Lee, Lee-Sup Kim
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. ISCAS (2015)