Akira Yamawaki

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 26

Top Topics

Bilateral Filtering

General Purpose

Top Venues

Artif. Life Robotics

Publications

Honoka Tani, Akira Yamawaki
Memory Access Optimization for Former Process of Pencil Drawing Style Image Conversion in High-Level Synthesis. PDCAT (2022)
Kilryong Lee, Akira Yamawaki
Background scrolling in high-level synthesis oriented game programing library. Artif. Life Robotics 27 (3) (2022)
Atsushi Shojima, Akira Yamawaki
Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration. Artif. Life Robotics 27 (3) (2022)
Kohei Shinyamada, Akira Yamawaki
Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction. Artif. Life Robotics 27 (3) (2022)
Kilryong Lee, Akira Yamawaki
Omnidirectional Background Scrolling in High-Level Synthesis Oriented Game Programing Library. TENCON (2021)
Kohei Shinyamada, Akira Yamawaki
Development of High Performance Hardware by High-Level Synthesis of Median-Based Dynamic Background Subtraction Method with Multiple Line Buffers. TENCON (2021)
Yuki Yamagata, Akira Yamawaki
A performance evaluation of read/write burst transfer by high-level synthesizable software for the alpha blending processing. Artif. Life Robotics 25 (2) (2020)
Moena Yamasaki, Akira Yamawaki
Duplicating same argument of function to realize efficient hardware for high-level synthesis. Artif. Life Robotics 25 (2) (2020)
Moena Yamasaki, Akira Yamawaki
Effect of Parallel Processing by Duplicating Histogram in Automatic Image Binarization for High-Level Synthesis. PDCAT (2019)
Yuki Yamagata, Akira Yamawaki
Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library. PDCAT (2019)
Yuichi Morita, Sota Kono, Akira Yamawaki
Proposal of an ultrasonic sensor array with flexible and scalable organization. Artif. Life Robotics 24 (2) (2019)
Shan Lu, Hiroshi Kamabe, Jun Cheng, Akira Yamawaki
Unrestricted-Rate Parallel Random Input-Output Codes for Multilevel Flash Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Construction of Parallel Random I/O Codes Using Coset Coding with Hamming Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Yuki Yamagata, Akira Yamawaki
An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool. TENCON (2018)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
An Upper Bound on the Generalized Cayley Distance. ISITA (2018)
Moena Yamawasaki, Akira Yamawaki
Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation. TENCON (2018)
Akira Yamawaki, Seiichi Serikawa
A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining. IEICE Trans. Inf. Syst. (2) (2018)
Shan Lu, Hiroshi Kamabe, Jun Cheng, Akira Yamawaki
Construction of Unrestricted Rate Parallel Random Input Output Code. CoRR (2017)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Worst-Case Performance of ILIFC with Inversion Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Construction of parallel RIO codes using coset coding with hamming codes. ITW (2017)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Lower Bounds on the Number of Writing Operations by ILIFC with Inversion Cells. CoRR (2017)
Shan Lu, Hiroshi Kamabe, Jun Cheng, Akira Yamawaki
Construction of unrestricted-rate parallel random input-output code. ISIT (2017)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Lower bounds on the number of write operations by index-less indexed flash code with inversion cells. ISIT (2017)
Akira Yamawaki, Hiroshi Kamabe, Shan Lu
Construction of Parallel RIO Codes using Coset Coding with Hamming Codes. CoRR (2017)
Akira Yamawaki, Seiichi Serikawa
Battery Life Estimation of Sensor Node with Zero Standby Power Consumption. CSE/EUC/DCABES (2016)
Akira Yamawaki, Hiroshi Kamabe
Maximization of average number of rewriting of ILIFC with inversion operation. ISITA (2016)
Akira Yamawaki, Mayu Yamanaka, Seiichi Serikawa
A sensor node architecture with zero standby power on wireless sensor network. Artif. Life Robotics 20 (3) (2015)
Huimin Lu, Yujie Li, Lifeng Zhang, Akira Yamawaki, Shiyuan Yang, Seiichi Serikawa
Underwater optical image dehazing using guided trigonometric bilateral filtering. ISCAS (2013)
Akira Yamawaki, Seiichi Serikawa
A lightweight sensing method of tooth-touch sound for disabled person using remote controller. Artif. Life Robotics 17 (2) (2012)
Hiroyuki Tanabe, Kohei Miyata, Akira Yamawaki, Seiichi Serikawa
A generic SoC platform using DPR feature to improve social life. SII (2012)
Akira Yamawaki, Seiichi Serikawa
An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA. ERSA (2010)
Akira Yamawaki, Takayuki Katakami, Yuhki Kitazono, Seiichi Serikawa
A method using the same light sensor for detecting multiple events near a window in crimes involving intrusion into a home. Artif. Life Robotics 15 (1) (2010)
Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane
An Efficient Hardware Architecture from C Program with Memory Access to Hardware. ICCSA (2) (2010)
Akira Yamawaki, Masahiko Iwane
An intermediate hardware model with load/store unit for C to FPGA. FPGA (2009)
Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. ERSA (2009)
Akira Yamawaki, Kazuharu Morita, Masahiko Iwane
An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware. APCCAS (2008)
Akira Yamawaki, Masahiko Iwane
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. ICPADS (2007)
Akira Yamawaki, Masahiko Iwane
A Programmable Load/Store Unit on C-based Hardware Design for FPGA. FPT (2007)
Akira Yamawaki, Masahiko Iwane
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ISPAN (2005)
Akira Yamawaki, Masahiko Iwane
An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. Circuits, Signals, and Systems (2005)
Akira Yamawaki, Masahiko Iwane
Evaluation of mechanisms introduced to improve performance of TSVM cache. Parallel and Distributed Computing and Networks (2004)
Akira Yamawaki, Masahiko Iwane
Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. ICPADS (2002)
Masahiko Iwane, Akira Yamawaki, Makoto Tanaka
Tagged communication and synchronization memory for multiprocessor-on-a-chip. Systems and Computers in Japan 32 (4) (2001)