An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor.
Akira YamawakiMasahiko IwanePublished in: Circuits, Signals, and Systems (2005)
Keyphrases
- parallel processing
- computational power
- multithreading
- level parallelism
- multiple queries
- processing speed
- distributed processing
- main memory
- shared memory multiprocessor
- memory hierarchy
- shared memory multiprocessors
- ibm sp
- parallel architectures
- parallel computation
- memory access
- cache conscious
- memory requirements
- processing units
- cache misses
- data access
- distributed memory
- parallel computers
- computer architecture
- prefetching
- memory subsystem
- data structure