Masahiko Iwane

Publication Activity (10 Years)

Years Active: 1992-2010
Publications (10 Years): 0

Publications

Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane
An Efficient Hardware Architecture from C Program with Memory Access to Hardware. ICCSA (2) (2010)
Akira Yamawaki, Masahiko Iwane
An intermediate hardware model with load/store unit for C to FPGA. FPGA (2009)
Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. ERSA (2009)
Akira Yamawaki, Kazuharu Morita, Masahiko Iwane
An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware. APCCAS (2008)
Akira Yamawaki, Masahiko Iwane
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. ICPADS (2007)
Akira Yamawaki, Masahiko Iwane
A Programmable Load/Store Unit on C-based Hardware Design for FPGA. FPT (2007)
Akira Yamawaki, Masahiko Iwane
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ISPAN (2005)
Akira Yamawaki, Masahiko Iwane
An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. Circuits, Signals, and Systems (2005)
Akira Yamawaki, Masahiko Iwane
Evaluation of mechanisms introduced to improve performance of TSVM cache. Parallel and Distributed Computing and Networks (2004)
Akira Yamawaki, Masahiko Iwane
Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. ICPADS (2002)
Masahiko Iwane, Akira Yamawaki, Makoto Tanaka
Tagged communication and synchronization memory for multiprocessor-on-a-chip. Systems and Computers in Japan 32 (4) (2001)
Masahiko Iwane
Extracting distance from defocused images with different aperture sizes. Systems and Computers in Japan 23 (10) (1992)