An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.
Akira YamawakiMasahiko IwanePublished in: ICPADS (2007)
Keyphrases
- fpga implementation
- hardware implementation
- shared memory multiprocessor
- hardware and software
- embedded systems
- field programmable gate array
- multithreading
- prefetching
- shared memory multiprocessors
- multiprocessor systems
- power consumption
- scheduling algorithm
- hardware software partitioning
- neural network
- main memory
- design methodology
- design space exploration
- query processing
- information systems
- pattern recognition
- distributed memory
- data access
- transfer function
- low cost
- image quality
- real time