Ajit Pal

Publication Activity (10 Years)

Years Active: 1986-2016
Publications (10 Years): 1

Top Topics

Formal Verification

Energy Efficient

Top Venues

J. Low Power Electron.

Opt. Switch. Netw.

Publications

Prasanta Majumdar, Ajit Pal, Tanmay De
Extending light-trail into elastic optical networks for dynamic traffic grooming. Opt. Switch. Netw. 20 (2016)
Subhendu Barat, Ajit Pal, Tanmay De
A load balanced approach of multicast routing and wavelength assignment in WDM networks. Int. J. Commun. Networks Distributed Syst. 15 (1) (2015)
Sumanta Pyne, Ajit Pal
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence. J. Low Power Electron. 11 (2) (2015)
Sumanta Pyne, Ajit Pal
Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating. J. Low Power Electron. 11 (1) (2015)
Sumanta Pyne, Ajit Pal
Loop unrolling with fine grained power gating for runtime leakage power reduction. VDAT (2014)
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis. J. Low Power Electron. 9 (3) (2013)
Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Sumanta Pyne, Ajit Pal
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence. VDAT (2013)
Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee
Formal Verification of Hardware / Software Power Management Strategies. VLSI Design (2013)
Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal
Formal Verification of Architectural Power Intent. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture CoRR (2013)
Sumanta Pyne, Ajit Pal
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques. J. Low Power Electron. 8 (5) (2012)
Rajdeep Mukherjee, Priyankar Ghosh, N. Sravan Kumar, Pallab Dasgupta, Ajit Pal
Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework. ISED (2012)
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture. ACITY (3) (2012)
Tanmay De, Puneet Jain, Ajit Pal
Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks. Photonic Netw. Commun. 21 (2) (2011)
Mallikarjuna Rao Nimmagadda, Ajit Pal
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. ISVLSI (2011)
Sukanta Bhattacharya, Tanmay De, Ajit Pal
An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy. ICDCN (2011)
Tanmay De, Ajit Pal, Indranil Sengupta
Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning. Photonic Netw. Commun. 20 (2) (2010)
Sukanta Bhattacharya, Tanmay De, Ajit Pal
Traffic grooming in WDM mesh networks using dynamic path selection strategy. WOCN (2010)
Suman Paul, Subrata Nandi, Ajit Pal
Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm. ICDCN (2010)
Sudip Roy, Ajit Pal
A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation. J. Low Power Electron. 6 (1) (2010)
Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. DAC (2010)
Ajit Pal, Santanu Chattopadhyay
Synthesis & Testing for Low Power. VLSI Design (2009)
Tanmay De, Ajit Pal, Indranil Sengupta
Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. ICDCN (2008)
Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta
A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks. ICIIS (2008)
Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta
A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks. ICON (2008)
Sudip Roy, Ajit Pal
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? DSD (2008)
Sujan Kundu, Sudip Roy, Ajit Pal
A power-aware wireless sensor network based bridge monitoring system. ICON (2008)
Akepati Sravan, Sujan Kundu, Ajit Pal
Low Power Sensor Node for a Wireless Sensor Network. VLSI Design (2007)
Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya
On finding the minimum test set of a BDD-based circuit. ACM Great Lakes Symposium on VLSI (2006)
Gopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. APCCAS (2006)
Maitrali Marik, Ajit Pal
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. VLSI Design (2004)
Debasis Samanta, Ajit Pal
Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design (2004)
Ajit Pal, Umesh Patel
Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. IWDC (2004)
Debasis Samanta, M. C. Dharmadeep, Ajit Pal
Synthesis of high performance low power PTL circuits. ASP-DAC (2003)
Debasis Samanta, Ajit Pal
Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design (2003)
Debasis Samanta, Ajit Pal
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. VLSI Design (2002)
Debasis Samanta, Nishant Sinha, Ajit Pal
Synthesis of High Performance Low Power Dynamic CMOS Circuits. VLSI Design (2002)
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design (2001)
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal
An algorithm for finding a non-trivial lower bound for channel routing1. Integr. 25 (1) (1998)
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. VLSI Design (1997)
Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
Computing area and wire length efficient routes for channels. VLSI Design (1995)
Rajat Kumar Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
A general graph theoretic framework for multi-layer channel routing. VLSI Design (1995)
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. VLSI Design (1993)
Rajat Kumar Pal, Ajit Pal
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing. VLSI Design (1992)
Ajit Pal
An Algorithm for Optimal Logic Design Using Multiplexers. IEEE Trans. Computers 35 (8) (1986)