Aijiao Cui

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 32

Top Topics

Linear Functions

Watermarking Scheme

Top Venues

IEEE Trans. Inf. Forensics Secur.

Publications

Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu
A Low-overhead PUF-based Secure Scan Design. ISQED (2023)
Renchao Li, Zhen Weng, Aijiao Cui, Gang Qu
A Lightweight Authentication Scheme with PE-Based Unclonable Label. AsianHOST (2023)
Mengqiang Lu, Aijiao Cui, Yan Shao, Gang Qu
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks. ACM Great Lakes Symposium on VLSI (2022)
Omid Aramoon, Gang Qu, Aijiao Cui
Building Hardware Security Primitives Using Scan-based Design-for-Testability. MWSCAS (2022)
Aijiao Cui, Zhen Weng, Hui Zhang, Gang Qu, Huawei Li
SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Aijiao Cui, Chip-Hong Chang, Wei Zhou, Yue Zheng
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Aijiao Cui, Chengkang He, Chip-Hong Chang, Hao Lu
Identification of FSM State Registers by Analytics of Scan-Dump Data. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Qidong Wang, Aijiao Cui, Gang Qu
Identification of Counter Registers through Full Scan Chain. ITC-Asia (2021)
Zhenxing Chang, Aijiao Cui, Ziming Wang, Gang Qu
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs. ISQED (2021)
Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li
A New Secure Scan Design with PUF-based Key for Authentication. VTS (2020)
Aijiao Cui, Yuxi Wang
How to Retrieve PUF Response from a Fabricated Chip Securely? ISQED (2020)
Ziming Wang, Aijiao Cui, Gang Qu
A Low-Cost Fault Injection Attack Resilient FSM Design. SoCC (2020)
Zhichao Xu, Aijiao Cui, Gang Qu
A New Aging Sensor for the Detection of Recycled ICs. ACM Great Lakes Symposium on VLSI (2020)
Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Aijiao Cui, Yan Yang, Gang Qu, Huawei Li
A Secure and Low-overhead Active IC Metering Scheme. VTS (2019)
Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li
A Memristor-based Scan Hold Flip-Flop. NVMSA (2019)
Chengkang He, Aijiao Cui, Chip-Hong Chang
Identification of State Registers of FSM Through Full Scan by Data Analytics. AsianHOST (2019)
Peiqi Sun, Aijiao Cui
A New Pay-Per-Use Scheme for the Protection of FPGA IP. ISCAS (2019)
Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li
A New Scheme to Extract PUF Information by Scan Chain. ATS (2018)
Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li
A low-overhead PUF based on parallel scan design. ASP-DAC (2018)
Xi Chen, Zhaojun Lu, Gang Qu, Aijiao Cui
Partial Scan Design Against Scan-Based Side Channel Attacks. TrustCom/BigDataSE (2018)
Xi Chen, Omid Aramoon, Gang Qu, Aijiao Cui
Balancing Testability and Security by Configurable Partial Scan Design. ITC-Asia (2018)
Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu
Why current secure scan designs fail and how to fix them? Integr. 56 (2017)
Xi Chen, Gang Qu, Aijiao Cui
Practical IP watermarking and fingerprinting methods for ASIC designs. ISCAS (2017)
Xi Chen, Gang Qu, Aijiao Cui, Carson Dunbar
Scan chain based IP fingerprint and identification. ISQED (2017)
Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? ATS (2017)
Aijiao Cui, Yanhui Luo, Chip-Hong Chang
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks. IEEE Trans. Inf. Forensics Secur. 12 (2) (2017)
Xiaonan Huang, Aijiao Cui, Chip-Hong Chang
A new watermarking scheme on scan chain ordering for hard IP protection. ISCAS (2017)
Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li
A New Active IC Metering Technique Based on Locking Scan Cells. ATS (2017)
Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li
A new countermeasure against scan-based side-channel attacks. ISCAS (2016)
Lucheng He, Aijiao Cui, Mengyang Li, André Ivanov
An improved test power optimization method by insertion of linear functions. ISCAS (2016)
Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
An ultra-low overhead LUT-based PUF for FPGA. AsianHOST (2016)
Mingze Gao, Khai Lai, Jiliang Zhang, Gang Qu, Aijiao Cui, Qiang Zhou
Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators. CAD/Graphics (2015)
Aijiao Cui, Gang Qu, Yan Zhang
Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection. IEEE Trans. Inf. Forensics Secur. 10 (11) (2015)
Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov
A new decompressor with ordered parallel scan design for reduction of test data and test time. ISCAS (2015)
Linfeng Chen, Aijiao Cui, Chip-Hong Chang
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction. IEEE Trans. Computers 64 (12) (2015)
Aijiao Cui, Tingting Yu, Gang Qu, Mengyang Li
An improved scan design for minimization of test power under routing constraint. ISCAS (2015)
Mengyang Li, Aijiao Cui, Tingting Yu
An improved scan cell ordering method using the scan cells with complementary outputs. ISIC (2014)
Aijiao Cui, Wei Liang, Gang Qu
A low-overhead dynamic watermarking scheme on scan design for easy authentication. ISCAS (2014)
Ruiyi Sun, Yan Zhang, Aijiao Cui
A refined affine approximation method of multiplication for range analysis in word-length optimization. EURASIP J. Adv. Signal Process. 2014 (2014)
Linfeng Chen, Aijiao Cui
A power-efficient scan tree design by exploring the Q'-D connection. ISCAS (2013)
Yongxia Liu, Aijiao Cui
An Efficient Zero-Aliasing Space Compactor Based on Elementary Gates Combined with XOR Gates. CAD/Graphics (2013)
Aijiao Cui, Chip-Hong Chang
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. APCCAS (2012)
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr T. Abdel-Hamid
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Aijiao Cui, Chip-Hong Chang, Li Zhang
A hybrid watermarking scheme for sequential functions. ISCAS (2011)
Chip-Hong Chang, Aijiao Cui
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Aijiao Cui, Chip-Hong Chang
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. ISCAS (2009)
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Aijiao Cui, Chip-Hong Chang
Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS (2008)
Aijiao Cui, Chip-Hong Chang
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS (2007)
Aijiao Cui, Chip-Hong Chang
Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS (2006)
Aijiao Cui, Chip-Hong Chang
Stego-signature at logic synthesis level for digital design IP protection. ISCAS (2006)