Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
Aibin YanChaoping LaiYinlei ZhangJie CuiZhengfeng HuangJie SongJing GuoXiaoqing WenPublished in: IEEE Trans. Emerg. Top. Comput. (2021)
Keyphrases
- low cost
- nano scale
- low power
- nm technology
- power consumption
- single chip
- digital camera
- high speed
- hardware and software
- low power consumption
- vlsi circuits
- real time
- data acquisition
- image sensor
- high density
- ultra low power
- embedded systems
- directed graph
- digital signal processing
- optimal path
- flip flops
- tree structure
- data sets
- power reduction
- delay insensitive