Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits.

Anand V. Hudli Raghu V. Hudli

Published in: VLSI Design (1994)

Keyphrases

vlsi circuits
test generation
test cases
symbolic execution
quality assurance
design automation
test sequences
static analysis
low power
software testing
real time
hidden markov models
low cost
quality control
code coverage