3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections.
Katsuyuki SakumaPaul S. AndryCornelia K. TsangSteven L. WrightBing DangChirag S. PatelBucknell C. WebbJ. MariaEdmund J. SprogisS. K. KangRobert J. PolastreRaymond R. HortonJohn U. KnickerbockerPublished in: IBM J. Res. Dev. (2008)