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Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Jingjing Fu
Zuying Luo
Xianlong Hong
Yici Cai
Sheldon X.-D. Tan
Zhu Pan
Published in:
PATMOS (2004)
Keyphrases
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high speed
power dissipation
low cost
power consumption
low power
chip design
input output
power losses
multithreading
computational power
robust estimation
real time
high density
high frequency
physical design
infrared
signal processing
host computer
database