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Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.

Licai HaoYaling WangYunlong LiuShiyu ZhaoXinyi ZhangYang LiWenjuan LuChunyu PengQiang ZhaoYongliang ZhouChenghu DaiZhiting LinXiulong Wu
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2024)
Keyphrases
  • highly robust
  • low cost
  • low power
  • design process
  • single chip
  • feature selection
  • image processing
  • user interface
  • data points
  • signal processing
  • engineering design
  • high density