A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.
Dongsuk JeonQing DongYejoong KimXiaolong WangShuai ChenHao YuDavid T. BlaauwDennis SylvesterPublished in: VLSIC (2015)
Keyphrases
- face recognition
- power consumption
- nm technology
- power supply
- hd video
- cmos technology
- low power
- compute intensive
- power dissipation
- face images
- random access memory
- high speed
- human faces
- memory requirements
- silicon on insulator
- face databases
- discriminant analysis
- principal component analysis
- computer vision
- low cost
- high definition
- real time
- recognition rate
- sparse representation
- face detection
- circuit design
- low voltage
- local binary pattern
- design considerations
- video transmission
- random access
- write operations
- metal oxide semiconductor
- neural network