Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.
A. AsenovJie DingDave ReidPlamen AsenovSalvatore M. AmorosoFikru Adamu-LemaLouis GerrerPublished in: ISCAS (2015)
Keyphrases
- floating gate
- circuit design
- cmos technology
- high speed
- low power
- analog vlsi
- power consumption
- reliability assessment
- delay insensitive
- simulation model
- vlsi circuits
- real time
- simulation environment
- metal oxide semiconductor
- mixed signal
- logic circuits
- statistical information
- statistical models
- statistical analysis
- mobile phone
- low cost