Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design.
Sung-Mo KangRobert H. KrambeckHung-Fai Stephen LawPublished in: DAC (1982)
Keyphrases
- chip design
- random access memory
- micron cmos
- cmos technology
- nm technology
- design considerations
- circuit design
- low power
- flip flops
- power dissipation
- logic circuits
- single chip
- low cost
- high speed
- design methodology
- physical design
- modal logic
- logic synthesis
- power consumption
- logic programming
- analog to digital converter
- cmos image sensor
- delay insensitive
- low voltage
- asynchronous circuits
- embedded dram
- digital circuits
- built in self test
- image sensor
- control system
- functional verification
- shift register
- design process
- parallel processing
- memory access
- high density