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An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge.
Jaehoon Song
Hyunbean Yi
Juhee Han
Sungju Park
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2009)
Keyphrases
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high speed
low power
low cost
high density
test suite
analog vlsi
hardware software co design
learning process
statistical tests