Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.
Gurgen HarutyunyanSamvel K. ShoukourianYervant ZorianPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
- bit rate
- prediction error
- selection mechanism
- associative memory
- management system
- prediction accuracy
- communication protocol
- memory requirements
- network architecture
- fault detection
- fault diagnosis
- prediction model
- design considerations
- processing elements
- multithreading
- memory hierarchy
- real time
- software architecture
- memory usage
- computing power
- prediction algorithm
- computational model
- level parallelism