A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.
Dongsuk JeonQing DongYejoong KimXiaolong WangShuai ChenHao YuDavid T. BlaauwDennis SylvesterPublished in: IEEE J. Solid State Circuits (2017)
Keyphrases
- face recognition
- power consumption
- random access memory
- nm technology
- power supply
- high speed
- hd video
- cmos technology
- low power
- single chip
- dynamic random access memory
- embedded dram
- silicon on insulator
- read write
- power dissipation
- memory management
- discriminant analysis
- face images
- intel xeon
- memory subsystem
- low cost
- computer vision
- processing elements
- level parallelism
- memory requirements
- human faces
- memory hierarchy
- recognition rate
- chip design
- face detection
- feature extraction
- processor core
- power management
- facial images
- high definition
- memory access
- ibm power processor
- operating system
- metal oxide semiconductor
- random access
- low voltage
- flash memory
- parallel processing
- database workloads
- computing power
- principal component analysis
- circuit design