Low power test generation for path delay faults using stability functions.
Mahilchi Milir Vaseekar KumarSpyros TragoudasPublished in: ACM Great Lakes Symposium on VLSI (2005)
Keyphrases
- low power
- test generation
- test cases
- low cost
- high speed
- power consumption
- mutation testing
- power dissipation
- test sequences
- single chip
- wireless transmission
- vlsi circuits
- logic circuits
- digital signal processing
- vlsi architecture
- image sensor
- static analysis
- software testing
- quality assurance
- low power consumption
- cmos technology
- high power
- gate array
- power reduction
- mixed signal
- test suite
- training set
- multi agent systems