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A parallel ADC for high-speed CMOS image processing system with 3D structure.
Kouji Kiyoyama
Yuki Ohara
Kang Wook Lee
Y. Yang
Takafumi Fukushima
Tetsu Tanaka
Mitsumasa Koyanagi
Published in:
3DIC (2009)
Keyphrases
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high speed
image processing
low power
real time
pattern recognition
parallel processing
machine vision
digital image processing
frame rate
high speed networks
computer vision
feature extraction
multiscale
image enhancement
power consumption
structural information