Buffered clock tree sizing for skew minimization under power and thermal budgets.

Krit Athikulwongse Xin Zhao Sung Kyu Lim

Published in: ASP-DAC (2010)

Keyphrases

power consumption
power losses
tree structure
duty cycle
infrared
electrical power
objective function
high speed
binary tree
low power
tree construction
tree models
hierarchical structure
tree search
tree structures
buffer size
tree nodes
high temperature
electrical properties
spanning tree
solder ball connect