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A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Aibin Yan
Kuikui Qian
Tai Song
Zhengfeng Huang
Tianming Ni
Yu Chen
Xiaoqing Wen
Published in:
Integr. (2022)
Keyphrases
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low cost
low power
single chip
low power consumption
power consumption
cost effective
high speed
design process
user interface
engineering design
circuit design
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power reduction