Login / Signup
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Aibin Yan
Kuikui Qian
Tai Song
Zhengfeng Huang
Tianming Ni
Yu Chen
Xiaoqing Wen
Published in:
Integr. (2022)
Keyphrases
</>
low cost
low power
single chip
low power consumption
power consumption
cost effective
high speed
design process
user interface
engineering design
circuit design
digital camera
design principles
hardware and software
digital signal processing
power reduction