A Novel Functional Testing and Verification Technique for Logic Circuits.

Hussain Al-Asaad Ganesh Valliappan Lourdes Ramirez

Published in: CDES (2005)

Keyphrases

logic circuits
low power
functional verification
test generation
functional decomposition
symbolic execution
formal verification
model checking
logic synthesis
gate array
low cost
tunnel diode
computer vision
pattern recognition
test cases
inductive learning