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3D memory chip stacking by multi-layer self-assembly technology.
Takafumi Fukushima
Jichoel Bea
Mariappan Murugesan
Ho-Young Son
M.-S. Suh
K.-Y. Byun
N.-S. Kim
Kang Wook Lee
Mitsumasa Koyanagi
Published in:
3DIC (2013)
Keyphrases
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multi layer
memory subsystem
neural nets
feed forward neural networks
neural network
high speed
single layer
multiple layers
memory access
error back propagation
ibm zenterprise
embedded dram
learning process
generative model