Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.
Avik ChakrabortyPublished in: VLSI Design (2005)
Keyphrases
- test set
- logic synthesis
- error rate
- test data
- markov chain
- training set
- cellular automata
- test cases
- multi valued
- delay insensitive
- training data
- logic circuits
- evaluation methodology
- digital circuits
- asynchronous circuits
- analog circuits
- image processing
- random selection
- random access memory
- dermoscopy images
- software testing
- test data generation
- program synthesis
- class distribution
- modal logic
- high speed
- feature extraction