Young Hun Seo

Publication Activity (10 Years)

Years Active: 2009-2017
Publications (10 Years): 1

Top Topics

Error Diffusion

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Seunghwan Hong, Shinwoong Kim, Seungnam Choi, Hwasuk Cho, Jaehyeong Hong, Young Hun Seo, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Jun-Seok Kim, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS. IEEE J. Solid State Circuits 48 (2) (2013)
Dong-Woo Jee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC. IEEE J. Solid State Circuits 47 (4) (2012)
Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS. IEEE J. Solid State Circuits 47 (3) (2012)
Young Hun Seo, Seon-Kyoo Lee, Jae-Yoon Sim
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (2) (2011)
Seon-Kyoo Lee, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. ISSCC (2010)
Seon-Kyoo Lee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. IEEE J. Solid State Circuits 45 (12) (2010)
Young Hun Seo, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim
A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength. IEEE Trans. Circuits Syst. II Express Briefs (5) (2010)
Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
A Distortion-Free General Purpose LVDS Driver. IEICE Trans. Electron. (2) (2009)
Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. ISSCC (2009)