A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.

Seon-Kyoo Lee Young Hun Seo Yunjae Suh Hong-June Park Jae-Yoon Sim

Published in: ISSCC (2010)

Keyphrases

high speed
user friendly
power consumption
phase locked loop
low power
high resolution
minimum cost
low cost
circuit design
analog vlsi
end to end
low voltage