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A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS.
Seon-Kyoo Lee
Young Hun Seo
Hong-June Park
Jae-Yoon Sim
Published in:
IEEE J. Solid State Circuits (2010)
Keyphrases
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high speed
user friendly
power consumption
high resolution
low power
low cost
phase locked loop
frequency band
power law
low resolution
circuit design
delay insensitive
vlsi circuits
real time
response time
web services
power supply