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Yiqing Huang
Publication Activity (10 Years)
Years Active: 2007-2012
Publications (10 Years): 0
Top Topics
Video Conferencing
Pixel Domain
Mode Selection
Bitstream
Top Venues
IEICE Trans. Inf. Syst.
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Publications
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Lei Sun
,
Jie Leng
,
Jia Su
,
Yiqing Huang
,
Hiroomi Motohashi
,
Takeshi Ikenaga
Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing.
IEICE Trans. Inf. Syst.
(5) (2012)
Xiaocong Jin
,
Jun Sun
,
Jun Zhou
,
Yiqing Huang
,
Jia Su
,
Takeshi Ikenaga
Adaptive fast DIRECT mode decision algorithm using mode and Lagrangian cost prediction for B frame in H.264/AVC.
ICME
(2011)
Jia Su
,
Yiqing Huang
,
Lei Sun
,
Shinichi Sakaida
,
Takeshi Ikenaga
Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(10) (2011)
Xiaocong Jin
,
Jun Sun
,
Yiqing Huang
,
Jia Su
,
Takeshi Ikenaga
Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost.
IEICE Trans. Inf. Syst.
(8) (2011)
Jia Su
,
Yiqing Huang
,
Lei Sun
,
Shinichi Sakaida
,
Takeshi Ikenaga
Coarse to fine adaptive interpolation filter for high resolution video coding.
ICME
(2011)
Yiqing Huang
,
Xiaocong Jin
,
Jin Zhou
,
Jia Su
,
Takeshi Ikenaga
Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60 fps.
IEICE Trans. Electron.
(4) (2011)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation.
MMM
(2010)
Yiqing Huang
,
Takeshi Ikenaga
Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60 fps.
IEICE Trans. Electron.
(3) (2010)
Shuijiong Wu
,
Peilin Liu
,
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders.
IEICE Trans. Inf. Syst.
(7) (2010)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder.
DPS
(2009)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Highly parallel fractional motion estimation engine for Super Hi-Vision 4k×4k@60fps.
MMSP
(2009)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Fast inter mode decision algorithm based on macroblock and motion feature analysis for H.264/AVC video coding.
EUSIPCO
(2009)
Jingbang Qiu
,
Tianci Huang
,
Yiqing Huang
,
Takeshi Ikenaga
A Hardware Accelerator with Variable Pixel Representation & Skip Mode Prediction for Feature Point Detection Part of SIFT Algorithm.
MVA
(2009)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Macroblock Feature Based Adaptive Propagate Partial SAD Architecture for HDTV Application.
IPSJ Trans. Syst. LSI Des. Methodol.
2 (2009)
Yiqing Huang
,
Qin Liu
,
Satoshi Goto
,
Takeshi Ikenaga
VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(8) (2009)
Shuijiong Wu
,
Peilin Liu
,
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
On bit allocation and Lagrange Multiplier adjustment for rate-distortion optimized H.264 rate control.
MMSP
(2009)
Shuijiong Wu
,
Yiqing Huang
,
Takeshi Ikenaga
A Macroblock-Level Rate Control Algorithm for H.264/AVC Video Coding with Context-Adaptive MAD Prediction Model.
ICCMS
(2009)
Shuijiong Wu
,
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Rate-distortion optimized multi-stage rate control algorithm for H.264/AVC video coding.
EUSIPCO
(2009)
Yiqing Huang
,
Qin Liu
,
Shuijiong Wu
,
Zhewen Zheng
,
Takeshi Ikenaga
Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2009)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Macroblock feature and motion involved multi-stage fast inter mode decision algorithm in H.264/AVC video coding.
ICIP
(2009)
Yiqing Huang
,
Qin Liu
,
Satoshi Goto
,
Takeshi Ikenaga
Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.
ACM Great Lakes Symposium on VLSI
(2009)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Content aware configurable architecture for H.264/AVC integer motion estimation engine.
ICME
(2009)
Yiqing Huang
,
Qin Liu
,
Satoshi Goto
,
Takeshi Ikenaga
Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(11) (2009)
Qin Liu
,
Yiqing Huang
,
Satoshi Goto
,
Takeshi Ikenaga
Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(4) (2009)
Yiqing Huang
,
Satoshi Goto
,
Takeshi Ikenaga
VLSI friendly computation reduction scheme in H.264/AVC motion estimation.
ISCAS
(2008)
Qin Liu
,
Yiqing Huang
,
Takeshi Ikenaga
Early detection algorithms for 4×4 and 8×8 all-zero blocks in H.264/AVC.
EUSIPCO
(2008)
Yiqing Huang
,
Zhenyu Liu
,
Yang Song
,
Satoshi Goto
,
Takeshi Ikenaga
Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(4) (2008)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(10) (2008)
Qin Liu
,
Yiqing Huang
,
Satoshi Goto
,
Takeshi Ikenaga
Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(8) (2008)
Qin Liu
,
Yiqing Huang
,
Takeshi Ikenaga
Early detection algorithms for 8×8 all-zero blocks in H.264/AVC.
MMSP
(2008)
Yiqing Huang
,
Qin Liu
,
Takeshi Ikenaga
Compressor tree based processing element optimization in propagate partial SAD architecture.
APCCAS
(2008)
Zhenyu Liu
,
Yiqing Huang
,
Yang Song
,
Satoshi Goto
,
Takeshi Ikenaga
VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC.
EUSIPCO
(2007)
Zhenyu Liu
,
Yiqing Huang
,
Yang Song
,
Satoshi Goto
,
Takeshi Ikenaga
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.
ACM Great Lakes Symposium on VLSI
(2007)