Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
Yiqing HuangZhenyu LiuYang SongSatoshi GotoTakeshi IkenagaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2008)
Keyphrases
- variable block size motion estimation
- motion vectors
- parallel architecture
- block size
- motion estimation
- video coding
- motion compensation
- variable block size
- shared memory
- video sequences
- parallel processing
- high definition
- bit rate
- macroblock
- distributed memory
- reference frame
- block matching
- parallel implementation
- motion field
- compressed domain
- video data
- hardware implementation
- computational complexity
- video coding standard
- rate distortion
- motion compensated
- prediction error
- coding efficiency
- quadtree
- search range
- inter frame
- compressed video
- video streams
- motion estimator