Yinyin Lin

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 13

Top Topics

High Reliability

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Zixu Li, Wang Wang, Xin Zhong, Manni Li, Jiayu Yang, Yinyin Lin, Guhyun Kim, Yosub Song, Chengchen Wang, Xiankui Xiong
LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing. ISCAS (2024)
Wang Wang, Xin Zhong, Manni Li, Zixu Li, Yinyin Lin
ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation. IEEE Access 11 (2023)
Yarong Fu, Wang Wang, Xin Zhong, Manni Li, Zixu Li, Qing Dong, Yu Jiang, Yinyin Lin
Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Yarong Fu, Kai Yang, B. A. Chen, Yinyin Lin
3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance. Microelectron. J. 66 (2017)
Jianguo Yang, Yinyin Lin, Yarong Fu, Xiaoyong Xue, B. A. Chen
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. ISCAS (2017)
Weiliang Jing, Kai Yang, Yinyin Lin, Beomseop Lee, Sangkyu Yoon, Yong Ye, Yuan Du, Bomy Chen
Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. IEEE Trans. Computers 66 (5) (2017)
Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. ASICON (2017)
Yanqing Zhao, Juan Xu, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jaehwang Sim
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. ISCAS (2016)
Yinyin Lin, Xinyi Hu, Jianguo Yang, Xiaoyong Xue
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. ISCAS (2016)
Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs (4) (2016)
Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express 13 (7) (2016)
Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ASICON (2015)
Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. ISCAS (2015)
Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin
A low cost and high reliability true random number generator based on resistive random access memory. ASICON (2015)
Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. ASICON (2013)
Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. ASICON (2013)
Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. IEEE J. Solid State Circuits 48 (5) (2013)
Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. ASICON (2013)
Wenxiang Jian, Gang Jin, Na Yan, Zhongyu Bi, Hao Min, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
O-based RRAM for low power application. IEICE Electron. Express 9 (21) (2012)
Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express 9 (12) (2012)
Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. VLSIC (2012)
Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin
A BIST scheme for high-speed Gain Cell eDRAM. ASICON (2011)
Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin
Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON (2011)
Xiaoyong Xue, Yufeng Xie, Yinyin Lin
Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express 8 (7) (2011)
Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. (12) (2010)
Yang Hong, Yinyin Lin, Tingao Tang, Bomy Chen
Multilevel Storage in Phase-Change Memory. IEICE Trans. Electron. (3) (2007)
Feifei Liao, Yiqing Ding, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bomy Chen
thin film transistor and its application in non-volatile memory. Microelectron. J. 37 (8) (2006)
Hangbing Lv, Peng Zhou, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bingchu Cai, Bomy Chen
Electronic properties of GST for non-volatile memory. Microelectron. J. 37 (9) (2006)