Yasuaki Nishitani

Publication Activity (10 Years)

Years Active: 1981-2024
Publications (10 Years): 4

Top Topics

Firing Squad Synchronization

Top Venues

IEICE Trans. Inf. Syst.

Inf. Process. Lett.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 107 (8) (2024)
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL (2023)
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
New Two-Qubit Gate Library with Entanglement. ISMVL (2016)
Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. (9) (2014)
Kazuya Yamashita, Yasuaki Nishitani, Sadaki Hirose, Satoshi Okawa, Nobuyasu Osato
The firing squad synchronization problem with sub-generals. Inf. Process. Lett. 114 (1-2) (2014)
Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura
A Testable Realization for Decimal Multipliers. ISMVL (2011)
Kazuya Yamashita, Mitsuru Sakai, Sadaki Hirose, Yasuaki Nishitani
The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays. IEICE Trans. Inf. Syst. (12) (2010)
Takashi Hirayama, Yasuaki Nishitani
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions. J. Circuits Syst. Comput. 18 (3) (2009)
Takashi Hirayama, Yasuaki Nishitani
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions. DELTA (2006)
Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation. APCCAS (2006)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
A Faster Algorithm of Minimizing AND-EXOR Expressions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
A faster algorithm of minimizing AND-EXOR expressions. APCCAS (2) (2002)
Yoshihide Igarashi, Yasuaki Nishitani
Speedup of Lockout-Free Mutual Exclusion Algorithms. ISPAN (1999)
Yoshihide Igarashi, Yasuaki Nishitani
Speedup of the n-Process Mutual Exclusion Algorithm. Parallel Process. Lett. 9 (4) (1999)
Koji Obokata, Yasuaki Nishitani, Yoshihide Igarashi
A Probably Optimal Embedding of Hyper-Rings in Hypercubes. Inf. Process. Lett. 58 (3) (1996)
Takashi Hirayama, Yasuaki Nishitani
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions. Systems and Computers in Japan 27 (3) (1996)
Yukihiro Hamada, Aohan Mei, Yasuaki Nishitani, Yoshihide Igarashi
Embeddings of Hyper-Rings in Hypercubes. ISAAC (1995)
Yasuaki Nishitani, Kensuke Shimizu, Masahiko Nagumo
Graph representation of logic functions to design two-level MOS networks. Systems and Computers in Japan 23 (1) (1992)
T. Ito, Yasuaki Nishitani
On Universality of Concurrent Expressions with Synchronization Primitives. Theor. Comput. Sci. 19 (1982)
Yasuaki Nishitani, Namio Honda
The Firing Squad Synchronization Problem for Graphs. Theor. Comput. Sci. 14 (1981)