Takashi Hirayama

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 8

Top Topics

Polynomial Delay

Top Venues

IEICE Trans. Inf. Syst.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. 107 (8) (2024)
Shunta Terui, Katsuhisa Yamanaka, Takashi Hirayama, Takashi Horiyama, Kazuhiro Kurita, Takeaki Uno
Enumerating Empty and Surrounding Polygons. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (9) (2023)
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ISMVL (2023)
Taishu Ito, Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs. IEICE Trans. Inf. Syst. (3) (2022)
Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs. FAW (2020)
Katsuhisa Yamanaka, Shogo Kawaragi, Takashi Hirayama
Exact Exponential Algorithm for Distance-3 Independent Set Problem. IEICE Trans. Inf. Syst. (3) (2019)
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
New Two-Qubit Gate Library with Entanglement. ISMVL (2016)
Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. IEICE Trans. Inf. Syst. (9) (2014)
Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura
A Testable Realization for Decimal Multipliers. ISMVL (2011)
Takashi Hirayama
Let's make a tennis game!: introduction to game programming. SIGGRAPH ASIA Courses (2009)
Takashi Hirayama, Yasuaki Nishitani
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions. J. Circuits Syst. Comput. 18 (3) (2009)
Takashi Hirayama, Yasuaki Nishitani
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions. DELTA (2006)
Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation. APCCAS (2006)
Ryoji Ishikawa, Takashi Hirayama, Goro Koda, Kensuke Shimizu
New Three-Level Boolean Expression Based on EXOR Gates. IEICE Trans. Inf. Syst. (5) (2004)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
A Faster Algorithm of Minimizing AND-EXOR Expressions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
A faster algorithm of minimizing AND-EXOR expressions. APCCAS (2) (2002)
Ryoji Ishikawa, T. Igarashi, Takashi Hirayama, Kensuke Shimizu
Pseudocube-based expressions to enhance testability. APCCAS (2) (2002)
Ryoji Ishikawa, Goro Koda, Kensuke Shimizu, Takashi Hirayama
Exor Decomposition with Common Variables and its Application to Multiple-Output Networks. J. Circuits Syst. Comput. 9 (1-2) (1999)
Takashi Hirayama, Yasuaki Nishitani
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions. Systems and Computers in Japan 27 (3) (1996)