Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
Takashi HirayamaRin SuzukiKatsuhisa YamanakaYasuaki NishitaniPublished in: ISMVL (2023)
Keyphrases
- logic circuits
- lower bound
- upper bound
- low power
- np hard
- branch and bound algorithm
- branch and bound
- gate array
- functional decomposition
- lower and upper bounds
- cellular automata
- markov chain
- tunnel diode
- optimal solution
- neural network
- high speed
- logic synthesis
- objective function
- power consumption
- real time
- worst case
- pattern recognition
- case study