Xiang Gao

Publication Activity (10 Years)

Years Active: 2007-2015
Publications (10 Years): 1

Top Topics

Sequential Monte Carlo

Sampling Algorithm

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Xiang Gao, Eric A. M. Klumperink, Bram Nauta
Sub-sampling PLL techniques. CICC (2015)
Ramen Dutta, Eric A. M. Klumperink, Xiang Gao, Zhiyu Ru, Ronan A. R. van der Zee, Bram Nauta
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. IEEE Trans. Circuits Syst. II Express Briefs (7) (2013)
Eric A. M. Klumperink, Ramen Dutta, Zhiyu Ru, Bram Nauta, Xiang Gao
Jitter-Power minimization of digital frequency synthesis architectures. ISCAS (2011)
Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta
Spur-reduction techniques for PLLs using sub-sampling phase detection. ISSCC (2010)
Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. VLSI Design (2010)
Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. IEEE J. Solid State Circuits 45 (9) (2010)
Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta
. IEEE J. Solid State Circuits 44 (12) (2009)
Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta
A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS. ISSCC (2009)
Xiang Gao, Eric A. M. Klumperink, Paul F. J. Geraedts, Bram Nauta
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs (2) (2009)
Xiang Gao, Bram Nauta, Eric A. M. Klumperink
Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation. IEEE Trans. Circuits Syst. II Express Briefs (3) (2008)
Xiang Gao, Eric A. M. Klumperink, Bram Nauta
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. ISCAS (2007)