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Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.
Ramen Dutta
Tarun Kanti Bhattacharyya
Xiang Gao
Eric A. M. Klumperink
Published in:
VLSI Design (2010)
Keyphrases
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power consumption
low power
low cost
finite element
life cycle
chip design
high speed
end to end delay
power dissipation
data sets
analog vlsi
single chip
product design
minimum cost
packet loss
social networks
circuit design
product information
power supply
real time
silicon on insulator