Wolfgang Günther

Publication Activity (10 Years)

Years Active: 1998-2006
Publications (10 Years): 0

University of Freiburg, Freiburg im Breisgau, Germany (PHD)

Education History

University of Freiburg, Freiburg im Breisgau, Germany

PHD

Publications

Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal Hypergraph Drawing for Improved Visibility. J. Graph Algorithms Appl. 10 (2) (2006)
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. VLSI Design (2005)
Wolfgang Günther, Stefan Höreth
Some Common Synthesis-Simulation-Mismatches. MBMV (2004)
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Minimization of the expected path length in BDDs based on local changes. ASP-DAC (2004)
Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal hypergraph routing for improved visibility. ACM Great Lakes Symposium on VLSI (2004)
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC (2004)
Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
Efficient (Non-)Reachability Analysis of Counterexamples. MBMV (2004)
Ilia Polian, Wolfgang Günther, Bernd Becker
Pattern-based verification of connections to intellectual property cores. Integr. 35 (1) (2003)
Wolfgang Günther, Rolf Drechsler
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52 (9) (2003)
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
Recursive bi-partitioning of netlists for large number of partitions. J. Syst. Archit. 49 (12-15) (2003)
Thomas Eschbach, Wolfgang Günther, Bernd Becker
Cross Reduction for Orthogonal Circuit Visualization. VLSI (2003)
Ilia Polian, Wolfgang Günther, Bernd Becker
The Case for 2-POF. MBMV (2003)
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (12) (2003)
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Combination of Lower Bounds in Exact BDD Minimization. DATE (2003)
Wolfgang Günther, Rolf Drechsler
Minimization of free BDDs. Integr. 32 (1-2) (2002)
Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
Crossing Reduction by Windows Optimization. Graph Drawing (2002)
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD (2002)
Rolf Drechsler, Wolfgang Günther, Stefan Höreth
Minimization of Word-Level Decision Diagrams. Integr. 33 (1-2) (2002)
Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. VLSI Design 2002 (1) (2002)
Rolf Drechsler, Wolfgang Günther
History-based dynamic BDD minimization. Integr. 31 (1) (2001)
Ilia Polian, Wolfgang Günther, Bernd Becker
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. MBMV (1) (2001)
Wolfgang Günther, Rolf Drechsler
Performance Driven Optimization for MUX based FPGAs. VLSI Design (2001)
Wolfgang Günther, Rolf Drechsler
Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design (2001)
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL (2001)
Wolfgang Günther, Andreas Hett, Bernd Becker
Application of linearly transformed BDDs in sequential verification. ASP-DAC (2001)
Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
Level Assignment for Displaying Combinational Logic. DSD (2001)
Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
Using lower bounds during dynamic BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD (2001)
Ilia Polian, Wolfgang Günther, Bernd Becker
Efficient Pattern-Based Verification of Connections to IP Cores . Asian Test Symposium (2001)
Wolfgang Günther, Rolf Drechsler
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. J. Syst. Archit. 46 (14) (2000)
Rolf Drechsler, Wolfgang Günther, Bernd Becker
Testability of Circuits Derived from Lattice Diagrams. LATW (2000)
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
Dynamic Re-Encoding During MDD Minimization. ISMVL (2000)
Wolfgang Günther, Rolf Drechsler, Stefan Höreth
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD (2000)
Rolf Drechsler, Wolfgang Günther
Optimization of sequential verification by history-based dynamic minimization of BDDs. ISCAS (2000)
Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor
-Layer Straightline Crossing Minimization by Speeding Up Sifting. Graph Drawing (2000)
Wolfgang Günther, Rolf Drechsler
Improving EAs for Sequencing Problems. GECCO (2000)
Rolf Drechsler, Wolfgang Günther
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO (2000)
Dragan Jankovic, Wolfgang Günther, Rolf Drechsler
Lower Bound Sifting for MDDs. ISMVL (2000)
Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
A Method for Approximate Equivalence Checking. ISMVL (2000)
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Fast exact minimization of BDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (3) (2000)
Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
Verification of Designs Containing Black Boxes. EUROMICRO (2000)
Wolfgang Günther, Rolf Drechsler
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO (2000)
Wolfgang Günther, Rolf Drechsler
On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75 (3) (2000)
Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
Verification of Designs Containing Black Boxes. MBMV (2000)
Rolf Drechsler, Wolfgang Günther, Bernd Becker
Testability of Circuits Derived from Lattice Diagrams. EUROMICRO (2000)
Nicole Drechsler, Wolfgang Günther, Rolf Drechsler
Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days (1999)
Wolfgang Günther, Rolf Drechsler
Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) (1999)
Rolf Drechsler, Wolfgang Günther
History-Based Dynamic Minimization During BDD Construction. VLSI (1999)
Wolfgang Günther, Rolf Drechsler
Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) (1999)
Wolfgang Günther, Rolf Drechsler
Efficient manipulation algorithms for linearly transformed BDDs. ICCAD (1999)
Wolfgang Günther, Rolf Drechsler
Minimization of Free BDDs. ASP-DAC (1999)
Rolf Drechsler, Wolfgang Günther
Generation of Optimal Universal Logic Modules. EUROMICRO (1999)
Rolf Drechsler, Wolfgang Günther
Using Lower Bounds During Dynamic BDD Minimization. DAC (1999)
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Fast Exact Minimization of BDDs. DAC (1998)
Wolfgang Günther, Rolf Drechsler
Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI (1998)

Wolfgang Günther.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Wolfgang Günther