Viveka Konandur Rajanna

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 14

Top Topics

Protection Schemes

Memory Capacity

Tactile Sensing

Top Venues

VLSI Technology and Circuits

IEEE J. Solid State Circuits

Publications

Viveka Konandur Rajanna
Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads. iSES (2023)
Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems. ESSCIRC (2023)
Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits (2023)
Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. VLSI Technology and Circuits (2023)
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. IEEE J. Solid State Circuits 57 (1) (2022)
Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. CICC (2022)
Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks. VLSI Technology and Circuits (2022)
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
and 749-1, 459 TOPS/W in 28nm. ESSDERC (2021)
Prachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto
per Receptor for Scaling to Human-Like Tactile Sensing Density. VLSI Circuits (2021)
Viveka Konandur Rajanna, Massimo Alioto
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications. IEEE J. Solid State Circuits 56 (11) (2021)
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
and 749-1, 459 TOPS/W in 28nm. ESSCIRC (2021)
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. ISSCC (2021)
Viveka Konandur Rajanna, Massimo Alioto
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications. CICC (2019)
Viveka Konandur Rajanna, Bharadwaj Amrutur
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)