Vinita Vasudevan

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 23

Top Topics

Loopy Belief Propagation

Singular Value Decomposition

Digital Signal Processing

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

ACM Trans. Design Autom. Electr. Syst.

Publications

Shivani Bathla, Vinita Vasudevan
Approximate inference of marginals using the IBIA framework. NeurIPS (2023)
Shivani Bathla, Vinita Vasudevan
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function. Trans. Mach. Learn. Res. 2023 (2023)
Shivani Bathla, Vinita Vasudevan
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function. CoRR (2023)
Shivani Bathla, Vinita Vasudevan
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Shivani Bathla, Vinita Vasudevan
Approximate inference of marginals using the IBIA framework. CoRR (2023)
V. Charumathi, M. Ramakrishna, Vinita Vasudevan
Fast and Accurate Proper Orthogonal Decomposition using Efficient Sampling and Iterative Techniques for Singular Value Decomposition. ACM Trans. Math. Softw. 48 (2) (2022)
Shivani Bathla, Vinita Vasudevan
IBIA: Bayesian Inference via Incremental Build-Infer-Approximate operations on Clique Trees. CoRR (2022)
Shivani Bathla, Vinita Vasudevan
MPE inference using an Incremental Build-Infer-Approximate Paradigm. CoRR (2022)
Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan
Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders. ACM Trans. Embed. Comput. Syst. 20 (2) (2021)
Basava Naga Girish Koneru, Nitin Chandrachoodan, Vinita Vasudevan
A Smoothed LASSO-Based DNN Sparsification Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. IET Comput. Digit. Tech. 15 (2) (2021)
Charumathi V, M. Ramakrishna, Vinita Vasudevan
Fast and Accurate Proper Orthogonal Decomposition using Efficient Sampling and Iterative Techniques for Singular Value Decomposition. CoRR (2020)
V. Charumathi, M. Ramakrishna, Vinita Vasudevan
Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition. CoRR (2019)
Basava Naga Girish Koneru, Vinita Vasudevan
Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
P. R. Chithira, Vinita Vasudevan
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. IEEE Trans. Very Large Scale Integr. Syst. 27 (6) (2019)
D. Celia, Vinita Vasudevan, Nitin Chandrachoodan
Optimizing power-accuracy trade-off in approximate adders. DATE (2018)
D. Celia, Vinita Vasudevan, Nitin Chandrachoodan
Probabilistic Error Modeling for Two-part Segmented Approximate Adders. ISCAS (2018)
Vinita Vasudevan, M. Ramakrishna
A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices. CoRR (2017)
P. R. Chithira, Vinita Vasudevan
A Hierarchical Technique for Statistical Path Selection and Criticality Computation. ACM Trans. Design Autom. Electr. Syst. 23 (1) (2017)
Ramprasath S., Madiwalar Vijaykumar, Vinita Vasudevan
A Skew-Normal Canonical Model for Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Ramprasath S., Vinita Vasudevan
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
S. Ramprasath, Vinita Vasudevan
An efficient algorithm for statistical timing yield optimization. DAC (2015)
Vinita Vasudevan, M. Ramakrishna
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form. DAC (2015)
S. Ramprasath, Vinita Vasudevan
Statistical Criticality Computation Using the Circuit Delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (5) (2014)
S. Ramprasath, Vinita Vasudevan
On the computation of criticality in statistical timing analysis. ICCAD (2012)
Vinita Vasudevan
Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2009)
K. N. Vikram, Vinita Vasudevan
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures. IEEE Trans. Very Large Scale Integr. Syst. 14 (9) (2006)
K. N. Vikram, Vinita Vasudevan
Scheduling divisible loads on partially reconfigurable hardware. FCCM (2006)
K. N. Vikram, Vinita Vasudevan
Hardware-software co-simulation of bus-based reconfigurable systems. Microprocess. Microsystems 29 (4) (2005)
Sunil Rafeeque, Vinita Vasudevan
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2005)
Vinita Vasudevan
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. DAC (2005)
Sunil Rafeeque, Vinita Vasudevan
A Built-in-Self-Test Scheme for Digital to Analog Converters. VLSI Design (2004)
Vinita Vasudevan
A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2004)
Sunil Rafeeque, Vinita Vasudevan
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. J. Electron. Test. 20 (6) (2004)
Sunil Rafeeque, Vinita Vasudevan
An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC. ISCAS (1) (2004)
Vinita Vasudevan
A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2004)
Vinita Vasudevan, M. Ramakrishna
Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2004)
Vinita Vasudevan
A time-domain technique for computation of noise spectral density in switched capacitor circuits. ISCAS (1) (2003)
Vinita Vasudevan, M. Ramakrishna
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. DAC (2003)
Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna
A Transistor Level Placement Tool for Custom Cell Generation. VLSI Design (2000)
Rajesh T. N. Rajaram, Vinita Vasudevan
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD. VLSI Design (2000)
C. F. Prince, Vinita Vasudevan
Symbolic Analysis of Analog Integrated Circuits. VLSI Design (1998)
Prakash Gopalakrishnan, Vinita Vasudevan
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. VLSI Design (1998)
K. Ravi Shanker, Vinita Vasudevan
Synthesis of Analog CMOS Circuits. VLSI Design (1997)