Ulrich Langmann

Publication Activity (10 Years)

Years Active: 1991-2008
Publications (10 Years): 0

Publications

Christopher Weyers, Pierre Mayr, Johannes W. Kunze, Ulrich Langmann
A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output. ISSCC (2008)
Thomas Suttorp, Ulrich Langmann
A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery. CICC (2007)
Marcus Schämann, Sebastian Hessel, Ulrich Langmann, Martin Bücker
Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system. DATE (2007)
Pierre Mayr, Christopher Weyers, Ulrich Langmann
A 90GHz 65nm CMOS Injection-Locked Frequency Divider. ISSCC (2007)
Marcus Schämann, Martin Bücker, Sebastian Hessel, Ulrich Langmann
Channel Equalization in HSDPA Receivers: Trade-Off between Performance and Complexity with a Variable Oversampling. VTC Spring (2006)
Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. IEEE J. Solid State Circuits 40 (3) (2005)
Frank Henkel, Ulrich Langmann
Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators. ISCAS (1) (2003)
Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama
A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. CICC (2003)
Frank Henkel, Ulrich Langmann, André Hanke, Stefan Heinen, Elmar Wagner
A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers. IEEE J. Solid State Circuits 37 (12) (2002)
Günter Grau, Ulrich Langmann, Wolfgang Winkler, Dieter Knoll, Jörg Osten, Klaus Pressel
A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications. IEEE J. Solid State Circuits 35 (9) (2000)
Tobias Ellermeyer, Ulrich Langmann, Berthold Wedding, Wolfgang Pöhlmann
A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver. IEEE J. Solid State Circuits 35 (12) (2000)
J. Christoph Scheytt, Gerhard Hanke, Ulrich Langmann
A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems. IEEE J. Solid State Circuits 34 (12) (1999)
Thorsten Baumheinrich, Ulrich Langmann
Design of high speed bipolar Si/SiGe ICs for optical wide band communications. ISCAS (2) (1999)
Oliver Kromat, Ulrich Langmann, Gerhard Hanke, William J. Hillery
A 10-Gb/s silicon bipolar IC for PRBS testing. IEEE J. Solid State Circuits 33 (1) (1998)
Thorsten Baumheinrich, Bernd Prégardier, Ulrich Langmann
A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC. IEEE J. Solid State Circuits 32 (11) (1997)
Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin
Si bipolar 14 Gb/s 1: 4-demultiplexer IC for system applications. IEEE J. Solid State Circuits 31 (1) (1996)
Bernd Prégardier, Ulrich Langmann, William J. Hillery
A 1.2-GS/s 8-b silicon bipolar track & hold IC. IEEE J. Solid State Circuits 31 (9) (1996)
Zhihao Lao, Ulrich Langmann
Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC. IEEE J. Solid State Circuits 31 (1) (1996)
Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin
A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems. IEEE J. Solid State Circuits 30 (2) (1995)
Ansgar Pottbaecker, Ulrich Langmann
An 8 GHz silicon bipolar clock-recovery and data-regenerator IC. IEEE J. Solid State Circuits 29 (12) (1994)
Zhigong Wang, Ulrich Langmann, Berthold G. Bosch
Multi-Gb/s Silicon Bipolar Clock Recovery IC. IEEE J. Sel. Areas Commun. 9 (5) (1991)