Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC.

Zhihao Lao Ulrich Langmann

Published in: IEEE J. Solid State Circuits (1996)

Keyphrases

low power
high speed
single chip
power consumption
low power consumption
logic circuits
gate array
low cost
digital signal processing
vlsi architecture
mixed signal
cmos technology
high power
long range
wireless transmission
real time
power reduction
delay insensitive