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Tsang-Chi Kan
Publication Activity (10 Years)
Years Active: 2010-2015
Publications (10 Years): 1
Top Topics
Axis Parallel
Design Decisions
Charge Coupled Device
Electrical Properties
Top Venues
ISQED
Circuits Syst. Signal Process.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Tsang-Chi Kan
,
Shanq-Jang Ruan
,
Ting-Feng Chang
,
Shih-Hsien Yang
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration.
Circuits Syst. Signal Process.
34 (10) (2015)
Tsang-Chi Kan
,
Ying-Jung Chen
,
Hung-Ming Hong
,
Shanq-Jang Ruan
Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(2) (2014)
Chih-han Hsu
,
Shanq-Jang Ruan
,
Ying-Jung Chen
,
Tsang-Chi Kan
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning.
ISQED
(2013)
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Ting-Feng Chang
,
Shanq-Jang Ruan
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate.
IEEE Trans. Very Large Scale Integr. Syst.
21 (1) (2013)
Tsang-Chi Kan
,
Hung-Ming Hong
,
Ying-Jung Chen
,
Shanq-Jang Ruan
Configurable redundant via-aware standard cell design considering multi-via mechanism.
ISQED
(2013)
Ting-Feng Chang
,
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Shanq-Jang Ruan
Enhanced Redundant via Insertion with Multi-via Mechanisms.
ISVLSI
(2011)
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Ting-Feng Chang
,
Shanq-Jang Ruan
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate.
ACM Great Lakes Symposium on VLSI
(2011)
Shanq-Jang Ruan
,
Tsang-Chi Kan
,
Jih-Chieh Hsu
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.
ACM Great Lakes Symposium on VLSI
(2010)