Toshio Sunaga

Publication Activity (10 Years)

Years Active: 1994-1997
Publications (10 Years): 0

Publications

Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi
An eight-bit prefetch circuit for high-bandwidth DRAM's. IEEE J. Solid State Circuits 32 (1) (1997)
Toshio Sunaga
A full bit prefetch DRAM sensing circuit. IEEE J. Solid State Circuits 31 (6) (1996)
Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter
A parallel processing chip with embedded DRAM macros. IEEE J. Solid State Circuits 31 (10) (1996)
Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira
A variable precharge voltage sensing. IEEE J. Solid State Circuits 30 (1) (1995)
Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura
A 64Kb - 32 DRAM for graphics applications. IBM J. Res. Dev. 39 (1-2) (1995)
Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter
Combined DRAM and logic chip for massively parallel systems. ARVLSI (1995)
Toshio Sunaga
A 30-ns cycle time 4-Mb mask ROM. IEEE J. Solid State Circuits 29 (11) (1994)