Combined DRAM and logic chip for massively parallel systems.

Peter M. Kogge Toshio Sunaga Hisatada Miyataka Koji Kitamura Eric Retter

Published in: ARVLSI (1995)

Keyphrases

massively parallel
parallel computing
high density
low cost
high performance computing
fine grained
high speed
computer systems
bayesian networks
objective function
distributed systems
computing systems
parallel machines
parallel architectures
digital circuits
chip design